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KS86C4302/C4304/P4304
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations.
KS86C4302/C4304 MICROCONTROLLER
The KS86C4302/C4304 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87Ri CPU core. The KS86C4302/C4304 is a versatile microcontroller, with its A/D converter, timer, PWM, and SIO it can be used in a wide range of general purpose applications. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The KS86C4302/C4304 have 2-Kbytes or 4Kbytes of program memory on-chip (ROM) and 112-bytes of general purpose register area RAM. Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core: -- Three configurable I/O ports (13 pins) -- Five interrupt sources with one vector and one interrupt level -- One 8-bit timer/counter with time interval mode -- Analog to digital converter with five input channels and 10-bit resolution -- One synchronous SIO module -- One 12-bit PWM output The KS86C4302/C4304 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC, and SIO. KS86C4302/C4304 is available in a 20/18/16-pin DIP and a 20-pin SOP package. OTP The KS86P4304 is an OTP (One Time Programmable) version of the KS86C4302/C4304 microcontroller. The KS86P4304 has on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The KS86P4304 is fully compatible with the KS86C4302/C4304, in function, in D.C. electrical characteristics and in pin configuration.
1-1
PRODUCT OVERVIEW
KS86C4302/C4304/P4304
FEATURES
CPU * SAM87RI CPU core Timer/Counters * * Memory * * 2/4-Kbyte internal program memory (ROM) 112-byte general purpose register area (RAM) PWM Module * Instruction Set * * 41 instructions The SAM87RI core provides all the SAM87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction. A/D Converter * * Five analog input pins 10-bit conversion resolution * 12-bit PWM 1-ch (Max: 250 kHz) 6-bit base + 6-bit extension frame One 8-bit basic timer for watchdog function One 8-bit timer/counter for the time interval mode
Instruction Execution Time * * 600 ns at 10 MHz fOSC (minimum cycles) 375 ns at 16 MHz fOSC (minimum cycles)
Buzzer Frequency Range * 200 Hz to 20 kHz signal can be generated
Oscillation Frequency * * * 1 MHz to 16 MHz external crystal oscillator Maximum 16 MHz CPU clock 4 MHz RC oscillator
Interrupts * 5 interrupt sources with one vector and one level interrupt structure
General I/O * * * Two I/O ports (Toatal 13 pins) One output only port (port 2) Bit programmable ports
Operating Temperature Range * - 40C to + 85C
Operating Voltage Range * 3.0 V to 5.5 V
Serial I/O * * One synchronius serial I/O module Selectable transmit and receive rates
OTP Interface Protocol Spec * Serial OTP
Built-in reset Circuit (LVD) * Low voltage detector for safe reset
Package Types * * * * 20-pin DIP-300 20-pin SOP-375 18-pin DIP-300 16-pin DIP-300
1-2
KS86C4302/C4304/P4304
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.3 BUZ, PWM, INT0, INT1
P1.0-P1.4 ADC0-ADC4 SCK, SO, SI, CLO
Basic Timer
Port 0
Port 1
XIN OSC XOUT
I/O Port and Interrupt Control
P0.2/T0CK Timer 0 Port 2
P2.0/SCK P2.1/SO P2.2 P2.3
P0.0/BUZ
BUZ
SAM87RI CPU
ADC0-ADC4 ADC
SIO
SCK (P1.3 or P2.0) SO (P1.2 or P2.1) SI (P1.1)
P0.1/PWM
PWM 2-KB ROM 4-KB ROM 112-Byte Register File
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
KS86C4302/C4304/P4304
PIN ASSIGNMENTS
VSS XIN XOUT TEST P0.2/T0CK/INT0 P0.1/PWM
RESET
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VDD P0.3/INT1 P1.0/ADC0 P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO P2.3
KS86C4302/ 4304
(TOP VIEW)
16 15 14 13 12 11
P0.0/BUZ P2.0/SCK P2.2
Figure 1-2. Pin Assignment Diagram (20-Pin DIP Package)
1-4
KS86C4302/C4304/P4304
PRODUCT OVERVIEW
VSS XIN XOUT TEST P0.2/T0CK/INT0 P0.1/PWM
RESET
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VDD P0.3/INT1 P1.0/ADC0 P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO P2.3
KS86C4302/ 4304
(TOP VIEW)
16 15 14 13 12 11
P0.0/BUZ P2.0/SCK P2.2
Figure 1-3. Pin Assignment Diagram (20-Pin SOP Package)
1-5
PRODUCT OVERVIEW
KS86C4302/C4304/P4304
VSS XIN XOUT TEST P0.2/T0CK/INT0 P0.1/PWM
RESET
1 2 3 4 5 6 7 8 9
18 17 16
VDD P0.3/INT1 P1.0/ADC0 P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO
KS86C4302/ 4304
(TOP VIEW)
15 14 13 12 11 10
P0.0/BUZ P2.0/SCK
Figure 1-4. Pin Assignment Diagram (18-Pin DIP Package)
VSS XIN XOUT TEST P0.2/T0CK/INT0 P0.1/PWM
RESET
1 2 3 4 5 6 7 8
16 15 14
VDD P0.3/INT1 P1.0/ADC0 P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF
KS86C4302/ 4304
(TOP VIEW)
13 12 11 10 9
P0.0/BUZ
Figure 1-5. Pin Assignment Diagram (16-Pin DIP Package)
1-6
KS86C4302/C4304/P4304
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. KS86C4302/C4304 Pin Descriptions Pin Names P0.0-P0.3 Pin Type I/O Pin Description Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors are assignable by software. Port 0 pins can also be used as alternative function. Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors are assignable by software. Port 1 pins can also be used as alternative function. Push-pull or open-drain output port. Pull up resistors are assignable by software. Port 2.0-2.1 pins can also be used as alternative function. Crystal/ceramic, or RC oscillator signal for system clock. System RESET signal input pin. Test signal input pin (for factory use only: must be connected to VSS) Voltage input pin and ground A/D converter reference voltage input and ground Bonded to VSS internally I/O O I O O O I I I Serial interface clock I/O Serial data output Serial data input System clock output port 200 Hz- 20 kHz frequency output for buzzer sound 12-bit PWM output External interrupt input port Timer 0 external clock input A/D converter input E-1 E-2 E-1 E-2 E-1 E-1 E E E E E-1 P1.3 or P2.0 P1.2 or P2.1 P1.1 P1.4 P0.0 P0.1 P0.2 P0.3 P0.2 P1.0-P1.4 Circuit Type E Share Pins BUZ PWM INT0/T0CK INT1 ADC0-ADC4 SI SO SCK CLO SCK SO - - - - -
P1.0-P1.4
I/O
E-1
P2.0-P2.3
O
E-2
XIN, XOUT
RESET
-
- B - - -
TEST VDD, VSS AVREF AVSS SCK SO SI CLO BUZ PWM INT0-INT1 T0CK ADC0-ADC4
I I - -
1-7
PRODUCT OVERVIEW
KS86C4302/C4304/P4304
PIN CIRCUITS
VDD
VDD
P-Channel Data In N-Channel Output DIsable
P-Channel Out N-Channel
Figure 1-6. Pin Circuit Type A
Figure 1-8. Pin Circuit Type C
VDD
VDD Pull-Up Resistor In
Pull-up Enable Data Output DIsable
P-Channel
Circuit Type C
I/O
Data
Figure 1-7. Pin Circuit Type B
Figure 1-9. Pin Circuit Type D
1-8
KS86C4302/C4304/P4304
PRODUCT OVERVIEW
VDD Open-Drain VDD Pull-up Resistor VDD Open-Drain VDD P-CH Output Data Output DIsable Pull-up Enable I/O N-CH Output Data Output DIsable N-CH Pull-up Resistor
P-CH
Pull-up Enable I/O
Input
Figure 1-10. Pin Circuit Type E
Figure 1-12. Pin Circuit Type E-2
VDD Open-Drain VDD Pull-up Resistor
P-CH Output Data Output DIsable
Pull-up Enable I/O
N-CH
Digital Input Analog Input
Figure 1-11. Pin Circuit Type E-1
1-9
PRODUCT OVERVIEW
KS86C4302/C4304/P4304
NOTES
1-10
KS86C4302/C4304/P4304
ELECTRICAL DATA
14
OVERVIEW
ELECTRICAL DATA
In this section, the following KS86C4302/C4304 electrical characteristics are presented in tables and graphs: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Input Timing Measurement Points -- Oscillator characteristics -- Oscillation stabilization time -- Operating Voltage Range -- Schmitt trigger input characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by a RESET -- A/D converter electrical characteristics -- LVD circuit characteristics -- LVD reset Timing -- Serial I/O timing characteristics -- Serial data transfer timing
14-1
ELECTRICAL DATA
KS86C4302/C4304/P4304
Table 14-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol VDD VI VO I OH I OL TA TSTG All input ports All output ports One I/O pin active All I/O pins active Output current low One I/O pin active All I/O pins active Operating temperature Storage temperature - - Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 25 - 80 + 30 + 150 - 40 to + 85 - 65 to + 150
C C
Unit V V V mA
mA
Table 14-2. DC Electrical Characteristics (TA = - 40C to + 85C, VDD = 3.0 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 Input low voltage VIL1 VIL2 Output high voltage Output low voltage VOH VOL
RESET
Conditions Ports 0, 1, and XIN and XOUT Ports 0, 1, and
RESET
Min 0.8 VDD VDD - 0.1
Typ -
Max VDD
Unit V
VDD= 3.0 to 5.5 V
VDD= 3.0 to 5.5 V
-
-
0.2 VDD 0.1
V
XIN and XOUT IOH = - 10 mA ports 0, 1, 2 IOL = 25 mA port 0, 1, and 2 VDD= 4.5 to 5.5 V VDD= 4.5 to 5.5 V VDD - 1.5 - VDD - 0.4 0.4
- 2.0
V V
14-2
KS86C4302/C4304/P4304
ELECTRICAL DATA
Table 14-2. DC Electrical Characteristics (Continued) (TA = - 40C to + 85C, VDD = 3.0 V to 5.5 V) Parameter Input high leakage current Symbol ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistors ILOH ILOL RP Conditions All inputs except ILIH2 VIN = VDD XIN, XOUT All inputs except ILIL2 and RESET XIN, XOUT All outputs All outputs VIN = 0 V Ports 0-2 VIN = VDD VIN = 0 V VIN = 0 V VOUT = VDD VOUT = 0 V VDD = 5 V VDD = 5 V Supply current IDD1 Run mode 16 MHz CPU clock 8 MHz CPU clock IDD2 Idle mode 16 MHz CPU clock 8 MHz CPU clock IDD3 Stop mode VDD = 5V 10% VDD = 3.3 V VDD = 5V 10% VDD = 3.3 V VDD = 5V 10% VDD = 3.3 V - - - - 30 100
-
Min -
Typ -
Max 1 20
Unit uA
-
-
-1 -20
uA
- - 47 200 11 3 5 0.7 65 45
2 -2 70 350 20 6 8 2.5 100 80
uA uA k
mA
uA
NOTE: D.C electrical values for supply current (IDD, to IDD3) do not include current drawn through internal pull-up resisters, output port drive current and ADC module.
14-3
ELECTRICAL DATA
KS86C4302/C4304/P4304
Table 14-3. AC Electrical Characteristics (TA = -40C to + 85C, VDD = 3.0 V to 5.5 V) Parameter Interrupt input high, low width input low width Symbol tINTH, tINTL tRSL Conditions INT0, INT1 VDD = 5V 10% Input VDD = 5V 10% Min - - Typ 200 1 Max - - Unit ns us
tINTL tRSL
tINTH
0.8 VDD 0.2 VDD
Figure 14-1. Input Timing Measurement Points
14-4
KS86C4302/C4304/P4304
ELECTRICAL DATA
Table 14-4. Oscillator Characteristics (TA = - 40C to + 85C) Oscillator Main crystal or ceramic Clock Circuit
XIN XOUT
Test Condition VDD = 4.5 to 5.5 V VDD = 3.0 to 4.5 V
Min 1 1
Typ - -
Max 16 8
Unit MHz
C1
C2
External clock
XIN
XOUT
VDD = 4.5 to 5.5 V VDD = 3.0 to 4.5 V
1 1
- -
16 8
RC oscillator
XIN R
XOUT
VDD = 5 V, R = 10 K VDD = 3 V, R = 22 K
- -
4 2
- -
Table 14-5. Oscillation Stabilization Time (TA = - 40C to + 85C, VDD = 3.0 V to 5.5 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time fOSC > 1.0 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low width (tXH, tXL) tWAIT when released by a reset (1) tWAIT when released by an interrupt (2) Test Condition Min - - 25 - - Typ - - - 216/fOSC - Max 20 10 500 - - ns ms Unit ms
NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the in the basic timer control register, BTCON. settings
14-5
ELECTRICAL DATA
KS86C4302/C4304/P4304
CPU Clock 16MHz 8MHz 4MHz 3MHz 2MHz 1MHz 1 2 2.7 3 4 5 5.5 6 7
Supply Voltage (V)
Figure 14-2. Operating Voltage Range
VOUT VDD
A = 0.2 VDD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD
VSS
A
B
C
D
VIN
0.3 VDD
0.7 VDD
Figure 14-3. Schmitt Trigger Input Characteristics Diagram
14-6
KS86C4302/C4304/P4304
ELECTRICAL DATA
Table 14-6. Data Retention Supply Voltage in Stop Mode (TA = - 40C to + 85C, VDD = 3.0 V to 5.5 V) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR = 2.0 V Min 2.0 - Typ - 0.1 Max 5.5 5 Unit V uA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Reset Occurs Stop Mode Data Retention Mode
Oscillation Stabilization Time Normal Operating Mode
~ ~ ~ ~
VDD
Execution Of Stop Instrction
RESET
VDDDR 0.8 VDD 0.2 VDD tWAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fosc
Figure 14-4. Stop Mode Release Timing When Initiated by a RESET
14-7
ELECTRICAL DATA
KS86C4302/C4304/P4304
Table 14-7. A/D Converter Electrical Characteristics (TA = - 40C to + 85C, VDD = 3.0 V to 5.5 V, VSS = 0 V) Parameter Total accuracy Symbol - Test Conditions VDD = 5.12 V CPU clock = 10 MHz AVREF = 5.12 V AVSS = 0 V Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) Analog input voltage Analog input impedance ADC reference voltage ADC reference ground Analog input current Analog block current (2) ILE DLE EOT EOB tCON VIAN RAN AVREF AVSS IADIN IADC - - - - fOSC = 10 MHz - - - - AVREF = VDD = 5 V AVREF = VDD = 5 V conversion time = 20 s AVREF = VDD = 3 V conversion time = 20 s AVREF = VDD = 5 V when power down mode - - - - - AVSS 2 3.0 VSS - - - 1 1 50x4/ fOSC - - - - - 1 2 1 3 2 - AVREF - VDD VSS + 0.3 10 3 s V M V V A mA Min - Typ - Max 3 Unit LSB
0.5
1.5
mA
100
500
nA
NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion.
14-8
KS86C4302/C4304/P4304
ELECTRICAL DATA
Table 14-8. LVD Circuit Characteristics (TA = - 40C to + 85C, VDD = 3.0 V to 5.5V) Parameter Power-on reset voltage high Power-on reset voltage low Power supply voltage rise time Power supply voltage off time Power-on reset circuit consumption current Symbol VDDH VDDL tr toff IDDPR VDD = 5 V 10 % VDD = 3 V Conditions Min 3.0 0 10 0.5 65 45 100 80 2.6 Typ Max 5.5 3.0
(note)
Unit V V us sec uA uA
NOTE: Oscillation stabilization time = 216/fx (= 6.55 ms at fx = 10 MHz)
VDD
VDDH
VDDL
tOFF
tR
Figure 14-5. LVD Reset Timing
14-9
ELECTRICAL DATA
KS86C4302/C4304/P4304
Table 14-9. Serial I/O Timing Characteristics (TA = - 40C to + 85C, VDD = 3.0 V to 5.5 V) Parameter Cycle Time Symbol tCKY tKH, tKL tSIK tKSI tKSO Conditions External Internal High, Low Width External Internal SI Setup Time to Low External Internal SI Hold Time to High External Internal Output Delay for to SO External Internal
NOTE: "
Min 1000 1000 500 tKCY/2 - 50 250 250 400 400 -
Typ -
Max -
Unit ns
source source source source source source source source source source
-
-
-
-
-
-
-
300 250
" means serial I/O clock frequency, "SI" means serial data input, and "SO" means serial data output.
tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input 0.2 VDD tKSO tKH
SO
Output Data
Figure 14-6. Serial Data Transfer Timing
14-10
KS86C4302/C4304/P4304
ELECTRICAL DATA
IDD1 (mA)
11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 5.0 VDD (V) fx = 8 MHz fx = 10 MHz fx = 16 MHz
Figure 14-7. IDD1 vs VDD
14-11
ELECTRICAL DATA
KS86C4302/C4304/P4304
VDD = 5.5 V IOL (mA) 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0.0 1.0 2.0 3.0 4.0 5.0 VOL (V) VDD = 4.5 V VDD = 5.0 V
Figure 14-8. IOL vs VOL
14-12
KS86C4302/C4304/P4304
ELECTRICAL DATA
IOH (mA)
-80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0.0 1.0 2.0 3.0 4.0 5.0 VOH (V) VDD = 5.0 V VDD = 5.5 V
VDD = 4.5 V
Figure 14-9. IOH vs VOH
14-13
ELECTRICAL DATA
KS86C4302/C4304/P4304
NOTES
14-14
KS86C4302/C4304/P4304
MECHANICAL DATA
15
OVERVIEW
MECHANICAL DATA
The KS86C4302/C4304 is available in a 20-pin SDIP package (Samsung: 20-DIP-300A), a 20-pin SOP package (Samsung: 20-SOP-375), a 18-pin DIP package (Samsung: 18-DIP-300A). Package dimensions are shown in Figure 15-1, 15-2, and 15-3.
#20
#11
0-15
6.40 0.20
#1
#10
26.80 MAX
0.20
26.40 0.20
0.51 MIN
0.46
0.10
(1.77)
1.52
0.10
2.54
NOTE :
Dimensions are in millimeters.
Figure 15-1. 20-DIP-300A Package Dimensions
3.30 0.30
5.08 MAX
3.25
0.2 + 5 - 0.10
0.0 5
20-DIP-300A
7.62
15-1
MECHANICAL DATA
KS86C4302/C4304/P4304
0-8 #20 #11
10.30 0.30
20-SOP-375
7.50
0.20
13.14 MAX
0.10
12.74 0.20
2.50 MAX
2.30
0.10 MAX
(0.66) 0.40
+ 0.10 - 0.05
1.27
NOTE :
Dimensions are in millimeters.
Figure 15-2. 20-SOP-375 Package Dimensions
15-2
0.05 MIN
0.85
0.203
0.20
#1
#10
+ 0.10 - 0.05
9.53
KS86C4302/C4304/P4304
MECHANICAL DATA
#18
#10
0-15
6.40 0.20
#1
#9
23.35 MAX
0.20
22.95 0.20
0.51 MIN
0.46
0.10
(1.32)
1.52
0.10
2.54
NOTE :
Dimensions are in millimeters.
Figure 15-3. 18-DIP-300A Package Dimensions
3.30 0.30
5.08 MAX
3.25
0.2 + 5 - 0.10
0.0 5
18-DIP-300A
7.62
15-3
MECHANICAL DATA
KS86C4302/C4304/P4304
#16
#9
6.40
7.62
#1
#8
19.80 3.25 5.08
0.38
(0.81)
1.50
2.54
Figure 15-4. 16-DIP-300A Package Dimensions
15-4
3.30
0.46
0.2 5
KS86C4302/C4304/P4304
KS86P4304 OTP
16
OVERVIEW
KS86P4304 OTP
The KS86P4304 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS86C4302/C4304 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS86P4304 is fully compatible with the KS86C4302/C4304, in function, in D.C. electrical characteristics, and in pin configuration. Because of its simple programming requirements, the KS86P4304 is ideal for use as an evaluation chip for the KS86C4302/C4304.
VSS/VSS XIN XOUT VPP/TEST P0.2/T0CK/INT0 P0.1/PWM
RESET/RESET
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16
VDD/VDD P0.3/INT1/SCLK P1.0/ADC0/SDAT P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO P2.3
KS86P4304
(TOP VIEW)
15 14 13 12 11
P0.0/BUZ P2.0/SCK P2.2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. Pin Assignment Diagram (20-Pin DIP Package)
16-1
KS86P4304 OTP
KS86C4302/C4304/P4304
VSS/VSS XIN XOUT VPP/TEST P0.2/T0CK/INT0 P0.1/PWM
RESET/RESET
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16
VDD/VDD P0.3/INT1/SCLK P1.0/ADC0/SDAT P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO P2.3
KS86P4304
(TOP VIEW)
15 14 13 12 11
P0.0/BUZ P2.0/SCK P2.2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-2. Pin Assignment Diagram (20-Pin SOP Package)
16-2
KS86C4302/C4304/P4304
KS86P4304 OTP
VSS/VSS XIN XOUT VPP/TEST P0.2/T0CK/INT0 P0.1/PWM
RESET/RESET
1 2 3 4 5 6 7 8 9
18 17 16 15
VDD/VDD P0.3/INT1/SCLK P1.0/ADC0/SDAT P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO
KS86P4304
(TOP VIEW)
14 13 12 11 10
P0.0/BUZ P2.0/SCK
NOTE:
The bolds indicate an OTP pin name.
Figure 16-3. Pin Assignment Diagram (18-Pin DIP Package)
16-3
KS86P4304 OTP
KS86C4302/C4304/P4304
VSS/VSS XIN XOUT VPP/TEST P0.2/T0CK/INT0 P0.1/PWM
RESET/RESET
1 2 3 4 5 6 7 8
16 15 14 13
VDD/VDD P0.3/INT1/SCLK P1.0/ADC0/SDAT P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF
KS86P4304
(TOP VIEW)
12 11 10 9
P0.0/BUZ
NOTE:
The bolds indicate an OTP pin name.
Figure 16-4. Pin Assingment Diagram (16-Pin DIP Package)
16-4
KS86C4302/C4304/P4304
KS86P4304 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.3 Pin Name SDAT Pin No. 18 (20-pin) 16 (18-pin) 19 (20-pin) 17 (18-pin) 4 During Programming I/O I/O Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned Serial clock pin (input only pin)
Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option)
P0.2 TEST
SCLK VPP (TEST)
I I
RESET
RESET
7 20 (20-pin), 18 (18-pin) 1 (20-pin), 1 (18-pin)
I I
Chip Initialization Logic power supply pin.
VDD/VSS
VDD/VSS
NOTE: ( ) means the SOP OTP pin number.
Table 16-2. Comparison of KS86P4304 and KS86C4302/C4304 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS86P4304 4 Kbyte EPROM 3.0 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 20 DIP/20 SOP/18 DIP User Program 1 time Programmed at the factory KS86C4302/C4304 2K/4K byte mask ROM 3.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the KS86P4304, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V
VPP
REG/MEM 0 0 0 1
ADDRESS
R/W 1 0 1 0
MODE EPROM read EPROM program EPROM verify EPROM read protection
(TEST) 5V 12.5 V 12.5 V 12.5 V
(A15-A0) 0000H 0000H 0000H 0E3FH
NOTE: "0" means Low level; "1" means High level.
16-5
KS86P4304 OTP
KS86C4302/C4304/P4304
NOTES
16-6

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